Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Liao, Chia-Chun | en_US |
dc.contributor.author | Lin, Min-Chen | en_US |
dc.contributor.author | Chiang, Tsung-Yu | en_US |
dc.contributor.author | Chao, Tien-Sheng | en_US |
dc.date.accessioned | 2014-12-08T15:38:10Z | - |
dc.date.available | 2014-12-08T15:38:10Z | - |
dc.date.issued | 2011 | en_US |
dc.identifier.issn | 1099-0062 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/26193 | - |
dc.identifier.uri | http://dx.doi.org/10.1149/1.3506399 | en_US |
dc.description.abstract | This paper investigates the impact of stress memorization on the interface-state for n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETS). We found that both the initial component of the deposited capping layer and the H released during annealing affected interface-state passivation. The annealed stress is responsible for degraded gate-leakage characteristics. Based on electrical performance and gate leakage, an initial compressive layer of SiN performs better than an initial tensile layer for the stress-memorization technique process. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3506399] All rights reserved. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Impact of Strain Layer on Gate Leakage and Interface-State for nMOSFETs Fabricated by Stress-Memorization Technique | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1149/1.3506399 | en_US |
dc.identifier.journal | ELECTROCHEMICAL AND SOLID STATE LETTERS | en_US |
dc.citation.volume | 14 | en_US |
dc.citation.issue | 1 | en_US |
dc.citation.spage | II30 | en_US |
dc.citation.epage | II32 | en_US |
dc.contributor.department | 電子物理學系 | zh_TW |
dc.contributor.department | Department of Electrophysics | en_US |
dc.identifier.wosnumber | WOS:000284317600020 | - |
dc.citation.woscount | 0 | - |
Appears in Collections: | Articles |