ANALYSIS OF BILATERAL LATCH-UP TRIGGERING IN VLSI CIRCUITS

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	HUANG, HS	en_US
dc.contributor.author	CHANG, CY	en_US
dc.contributor.author	HSU, CC	en_US
dc.contributor.author	CHEN, KL	en_US
dc.contributor.author	LIN, JK	en_US
dc.date.accessioned	2014-12-08T15:04:07Z	-
dc.date.available	2014-12-08T15:04:07Z	-
dc.date.issued	1994-02-01	en_US
dc.identifier.issn	0038-1101	en_US
dc.identifier.uri	http://hdl.handle.net/11536/2625	-
dc.language.iso	en_US	en_US
dc.title	ANALYSIS OF BILATERAL LATCH-UP TRIGGERING IN VLSI CIRCUITS	en_US
dc.type	Note	en_US
dc.identifier.journal	SOLID-STATE ELECTRONICS	en_US
dc.citation.volume	37	en_US
dc.citation.issue	2	en_US
dc.citation.spage	380	en_US
dc.citation.epage	382	en_US
dc.contributor.department	電控工程研究所	zh_TW
dc.contributor.department	Institute of Electrical and Control Engineering	en_US
dc.identifier.wosnumber	WOS:A1994MU89700020	-
dc.citation.woscount	0	-
顯示於類別：	期刊論文