完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Liao, Jie-Yu | en_US |
dc.contributor.author | Huang, Han-Hsiang | en_US |
dc.contributor.author | Chen, Ke-Horng | en_US |
dc.date.accessioned | 2014-12-08T15:38:43Z | - |
dc.date.available | 2014-12-08T15:38:43Z | - |
dc.date.issued | 2010 | en_US |
dc.identifier.isbn | 978-1-4244-5309-2 | en_US |
dc.identifier.issn | 0271-4302 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/26498 | - |
dc.description.abstract | The fast boost DC-DC converter designed with adaptive voltage positioning (AVP) technique to minimized the right-half plane zero effect is proposed. The concept of constant output impedance is a universal design principle in former works with AVP design. However, the right-half plane (RHP) zero appear in control to output transfer function of boost converter obstruct achievement of constant output impedance. The AC adjusting skill proposed in this paper illustrates how to obtain relative constant output impedance and accomplish the AVP characteristic in boost converter. The boost converter design with the AVP technique provides much faster response time and smaller voltage overshoots or undershoots during the load transient compared with any control scheme presented before. The simulation results is presented to show excellent performance of faster than 4 mu s response time and the 40mV voltage drop when the load current changes from 100mA to 400mA. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Minimized Right-Half Plane Zero Effect on Fast Boost DC-DC Converter Achieved by Adaptive Voltage Positioning Technique | en_US |
dc.type | Article | en_US |
dc.identifier.journal | 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS | en_US |
dc.citation.spage | 2916 | en_US |
dc.citation.epage | 2919 | en_US |
dc.contributor.department | 電控工程研究所 | zh_TW |
dc.contributor.department | Institute of Electrical and Control Engineering | en_US |
dc.identifier.wosnumber | WOS:000287216003036 | - |
顯示於類別: | 會議論文 |