標題: 2xVDD-Tolerant Power-Rail ESD Clamp Circuit With Low Standby Leakage in 65-nm CMOS Process
作者: Lin, Chun-Yu
Ker, Ming-Dou
電機學院
College of Electrical and Computer Engineering
公開日期: 2010
摘要: With the consideration of low standby leakage in nanoscale CMOS processes, a new 2xVDD-tolerant ESD clamp circuit was presented in this paper. The new ESD clamp circuit had a high-voltage-tolerant ESD detection circuit to improve the turn-on efficiency of the silicon-controlled-rectifier-based (SCR-based) ESD device. This design had been successfully verified in a 65-nm CMOS process. The leakage current of this ESD clamp circuit under normal circuit operating condition was only similar to 200 nA. Besides, this ESD clamp circuit can achieve 4.8-kV HBM ESD robustness. Therefore, this design was very suitable for mixed-voltage I/O interfaces in nanoscale CMOS processes.
URI: http://hdl.handle.net/11536/26521
ISBN: 978-1-4244-5309-2
ISSN: 0271-4302
期刊: 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS
起始頁: 3417
結束頁: 3420
Appears in Collections:Conferences Paper