Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Ho, SY | en_US |
| dc.contributor.author | Ho, SJ | en_US |
| dc.contributor.author | Lin, YK | en_US |
| dc.contributor.author | Chu, WCC | en_US |
| dc.date.accessioned | 2014-12-08T15:38:47Z | - |
| dc.date.available | 2014-12-08T15:38:47Z | - |
| dc.date.issued | 2004-08-01 | en_US |
| dc.identifier.issn | 1063-8210 | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/TVLSI.2004.831464 | en_US |
| dc.identifier.uri | http://hdl.handle.net/11536/26555 | - |
| dc.description.abstract | The conventional simulated annealing with some random generation mechanism using the sequence-pair topological representation in block placement and floorplanning is effective for a very small number of modules (40-50). This paper proposes an orthogonal simulated annealing algorithm (OSA) with an efficient generation mechanism (EGM) for solving large floorplanning problems. EGM samples a small number of representative floorplans and then efficiently derives a high-performance floorplan by using a systematic reasoning method for the next move of OSA based on orthogonal experimental design. Furthermore, an improved swap operation is proposed which cooperates with EGM to make OSA efficient. Excellent experimental results using the Microelectronics Center of North Carolina and the Gigascale Sysems Research Center benchmarks show that OSA performs better than existing methods for large floorplanning problems. | en_US |
| dc.language.iso | en_US | en_US |
| dc.subject | floorplanning | en_US |
| dc.subject | optimization | en_US |
| dc.subject | orthogonal experimental design | en_US |
| dc.subject | simulated annealing | en_US |
| dc.subject | very large scale integration (VLSI) | en_US |
| dc.title | An orthogonal simulated annealing algorithm for large floorplanning problems | en_US |
| dc.type | Article | en_US |
| dc.identifier.doi | 10.1109/TVLSI.2004.831464 | en_US |
| dc.identifier.journal | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | en_US |
| dc.citation.volume | 12 | en_US |
| dc.citation.issue | 8 | en_US |
| dc.citation.spage | 874 | en_US |
| dc.citation.epage | 876 | en_US |
| dc.contributor.department | 生物科技學系 | zh_TW |
| dc.contributor.department | 生物資訊及系統生物研究所 | zh_TW |
| dc.contributor.department | Department of Biological Science and Technology | en_US |
| dc.contributor.department | Institude of Bioinformatics and Systems Biology | en_US |
| dc.identifier.wosnumber | WOS:000222908800007 | - |
| dc.citation.woscount | 20 | - |
| Appears in Collections: | Articles | |
Files in This Item:
If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.

