標題: | A hierarchical N-queen decimation lattice and hardware architecture for motion estimation |
作者: | Wang, CN Yang, SW Liu, CM Chiang, TH 資訊工程學系 電子工程學系及電子研究所 Department of Computer Science Department of Electronics Engineering and Institute of Electronics |
關鍵字: | decimation lattice;fast motion estimation;hierarchical decimation lattice;N-Queen pattern;pixel decimation;video coding |
公開日期: | 1-四月-2004 |
摘要: | A subsampling structure, an N-Queen lattice, for spatially decimating a block of pixels is presented. Despite its use for many applications, we demonstrate that the N-Queen lattice can be used to speed up motion estimation with nominal loss of coding efficiency. With a simple construction, the N-Queen lattice characterizes the spatial features in the vertical, horizontal, and diagonal directions for both texture and edge areas. Especially in the 4-Queen case, every skipped pixel has the minimal and equal distance of unity to the selected pixel. It can be hierarchically organized for variable nonsquare block-size motion estimation. Despite the randomized lattice, we design compact data storage architecture for efficient memory access and simple hardware implementation. Our simulations show that the N-Queen lattice is superior to several existing sampling techniques with improvement in speed by about N times and small loss in peak SNR (PSNR). The loss in PSNR is negligible for slow-motion video sequences and is less than 0.45 M at worst for high-motion estimation sequences. |
URI: | http://dx.doi.org/10.1109/TCSVT.2004.825550 http://hdl.handle.net/11536/26908 |
ISSN: | 1051-8215 |
DOI: | 10.1109/TCSVT.2004.825550 |
期刊: | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY |
Volume: | 14 |
Issue: | 4 |
起始頁: | 429 |
結束頁: | 440 |
顯示於類別: | 期刊論文 |