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dc.contributor.authorWang, CNen_US
dc.contributor.authorYang, SWen_US
dc.contributor.authorLiu, CMen_US
dc.contributor.authorChiang, THen_US
dc.date.accessioned2014-12-08T15:39:24Z-
dc.date.available2014-12-08T15:39:24Z-
dc.date.issued2004-04-01en_US
dc.identifier.issn1051-8215en_US
dc.identifier.urihttp://dx.doi.org/10.1109/TCSVT.2004.825550en_US
dc.identifier.urihttp://hdl.handle.net/11536/26908-
dc.description.abstractA subsampling structure, an N-Queen lattice, for spatially decimating a block of pixels is presented. Despite its use for many applications, we demonstrate that the N-Queen lattice can be used to speed up motion estimation with nominal loss of coding efficiency. With a simple construction, the N-Queen lattice characterizes the spatial features in the vertical, horizontal, and diagonal directions for both texture and edge areas. Especially in the 4-Queen case, every skipped pixel has the minimal and equal distance of unity to the selected pixel. It can be hierarchically organized for variable nonsquare block-size motion estimation. Despite the randomized lattice, we design compact data storage architecture for efficient memory access and simple hardware implementation. Our simulations show that the N-Queen lattice is superior to several existing sampling techniques with improvement in speed by about N times and small loss in peak SNR (PSNR). The loss in PSNR is negligible for slow-motion video sequences and is less than 0.45 M at worst for high-motion estimation sequences.en_US
dc.language.isoen_USen_US
dc.subjectdecimation latticeen_US
dc.subjectfast motion estimationen_US
dc.subjecthierarchical decimation latticeen_US
dc.subjectN-Queen patternen_US
dc.subjectpixel decimationen_US
dc.subjectvideo codingen_US
dc.titleA hierarchical N-queen decimation lattice and hardware architecture for motion estimationen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/TCSVT.2004.825550en_US
dc.identifier.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGYen_US
dc.citation.volume14en_US
dc.citation.issue4en_US
dc.citation.spage429en_US
dc.citation.epage440en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000220612200003-
dc.citation.woscount28-
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