A CMOS 6-Bit 16-GS/s Time-Interleaved ADC with Digital Background Calibration

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DC Field	Value	Language
dc.contributor.author	Huang, Chun-Cheng	en_US
dc.contributor.author	Wang, Chung-Yi	en_US
dc.contributor.author	Wu, Jieh-Tsorng	en_US
dc.date.accessioned	2014-12-08T15:39:30Z	-
dc.date.available	2014-12-08T15:39:30Z	-
dc.date.issued	2010	en_US
dc.identifier.isbn	978-1-4244-7636-7	en_US
dc.identifier.uri	http://hdl.handle.net/11536/26965	-
dc.identifier.uri	http://dx.doi.org/10.1109/VLSIC.2010.5560312	en_US
dc.description.abstract	An 8-channel 6-bit 16-GS/s time-interleaved ADC was fabricated using a 65nm CMOS technology. Each A/D channel is a flash ADC using latch-type comparator with background offset calibration. Timing skews among the channels are also continuously calibrated in the background. The chip achieves 42.3dB SFDR and 30.8dB SNDR at 16 GS/s sampling rate.	en_US
dc.language.iso	en_US	en_US
dc.title	A CMOS 6-Bit 16-GS/s Time-Interleaved ADC with Digital Background Calibration	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/VLSIC.2010.5560312	en_US
dc.identifier.journal	2010 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS	en_US
dc.citation.spage	159	en_US
dc.citation.epage	160	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000287508300062	-
Appears in Collections:	Conferences Paper

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