An Interleaving Energy-Conservation Mode (IECM) Control in Single-Inductor Dual-Output (SIDO) Step-Down Converters with 91% Peak Efficiency

doi:10.1109/VLSIC.2010.5560272

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DC 欄位	值	語言
dc.contributor.author	Lee, Yu-Huei	en_US
dc.contributor.author	Chen, Ke-Horng	en_US
dc.contributor.author	Lin, Ying-Hsi	en_US
dc.contributor.author	Yang, Yao-Yi	en_US
dc.contributor.author	Wang, Shih-Jung	en_US
dc.contributor.author	Chen, Yi-Kuang	en_US
dc.contributor.author	Huang, Chen-Chih	en_US
dc.date.accessioned	2014-12-08T15:39:31Z	-
dc.date.available	2014-12-08T15:39:31Z	-
dc.date.issued	2010	en_US
dc.identifier.isbn	978-1-4244-7636-7	en_US
dc.identifier.uri	http://hdl.handle.net/11536/26976	-
dc.identifier.uri	http://dx.doi.org/10.1109/VLSIC.2010.5560272	en_US
dc.description.abstract	This interleaving energy-conservation mode control for single-inductor dual-output converter uses the superposition technique to yield the optimal average inductor current and 91% peak efficiency. Neither a freewheel stage nor a post-regulator is needed at nominal conditions. The output voltage ripple appears notably minimized over 50% by means of current interleaving at full load. The chip occupies 1.44 mm(2) in 65 nm CMOS and integrates with a 3D architecture for ultra-wide band system.	en_US
dc.language.iso	en_US	en_US
dc.title	An Interleaving Energy-Conservation Mode (IECM) Control in Single-Inductor Dual-Output (SIDO) Step-Down Converters with 91% Peak Efficiency	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/VLSIC.2010.5560272	en_US
dc.identifier.journal	2010 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS	en_US
dc.citation.spage	57	en_US
dc.citation.epage	58	en_US
dc.contributor.department	電控工程研究所	zh_TW
dc.contributor.department	Institute of Electrical and Control Engineering	en_US
dc.identifier.wosnumber	WOS:000287508300020	-
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