標題: | A new DLL-based approach for all-digital multiphase clock generation |
作者: | Chung, CC Lee, CY 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | delay-locked loops (DLLs);digitally controlled delay line (DCDL);multiphase clock generation;phase synchronization |
公開日期: | 1-三月-2004 |
摘要: | A new DLL-based approach for all-digital multiphase clock generation is presented. By-using the time-to-digital converter (TDC) with fixed-step search scheme, the proposed all-digital and cell-based solution can overcome the false-lock problem in conventional designs. Furthermore, the proposed all-digital multiphase clock generator (ADMCG) can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity in many different applications. The test chip shows that our proposal demonstrates a wide frequency range to meet the needs of many digital. communication applications. |
URI: | http://dx.doi.org/10.1109/JSSC.2003.822890 http://hdl.handle.net/11536/26981 |
ISSN: | 0018-9200 |
DOI: | 10.1109/JSSC.2003.822890 |
期刊: | IEEE JOURNAL OF SOLID-STATE CIRCUITS |
Volume: | 39 |
Issue: | 3 |
起始頁: | 469 |
結束頁: | 475 |
顯示於類別: | 期刊論文 |