A 5-GHz CMOS double-quadrature receiver front-end with single-stage quadrature generator

doi:10.1109/JSSC.2003.822779

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Wu, CY	en_US
dc.contributor.author	Chou, CY	en_US
dc.date.accessioned	2014-12-08T15:39:31Z	-
dc.date.available	2014-12-08T15:39:31Z	-
dc.date.issued	2004-03-01	en_US
dc.identifier.issn	0018-9200	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/JSSC.2003.822779	en_US
dc.identifier.uri	http://hdl.handle.net/11536/26982	-
dc.description.abstract	A 5-GHz CMOS double-quadrature front-end receiver for wireless LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals. Implemented in 0.18 mum CMOS technology, the receiver chip can achieve 50.6-dB image rejection with power dissipation of 22.4 mW at 1.8-V voltage supply.	en_US
dc.language.iso	en_US	en_US
dc.subject	CMOS technology	en_US
dc.subject	double-quadrature architecture	en_US
dc.subject	IEEE 802.11a	en_US
dc.subject	low-noise amplifier	en_US
dc.subject	quadrature generator	en_US
dc.subject	quadrature voltage-controlled oscillator	en_US
dc.subject	radio frequency	en_US
dc.subject	receiver	en_US
dc.title	A 5-GHz CMOS double-quadrature receiver front-end with single-stage quadrature generator	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/JSSC.2003.822779	en_US
dc.identifier.journal	IEEE JOURNAL OF SOLID-STATE CIRCUITS	en_US
dc.citation.volume	39	en_US
dc.citation.issue	3	en_US
dc.citation.spage	519	en_US
dc.citation.epage	521	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000220018900014	-
dc.citation.woscount	12	-
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