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dc.contributor.authorCheng, YLen_US
dc.contributor.authorWang, YLen_US
dc.contributor.authorLiu, CPen_US
dc.contributor.authorWu, YLen_US
dc.contributor.authorLo, KYen_US
dc.contributor.authorLiu, CWen_US
dc.contributor.authorLan, JKen_US
dc.contributor.authorAy, Cen_US
dc.contributor.authorFeng, MSen_US
dc.date.accessioned2014-12-08T15:39:44Z-
dc.date.available2014-12-08T15:39:44Z-
dc.date.issued2004-01-15en_US
dc.identifier.issn0254-0584en_US
dc.identifier.urihttp://dx.doi.org/10.1016/j.matchemphys.2003.08.023en_US
dc.identifier.urihttp://hdl.handle.net/11536/27135-
dc.description.abstractRecently, fluorosilicate glass (FSG) has received much attention for application in microelectronics manufacturing due to its low dielectric constant and stable gap-filling ability. Although FSG films have been demonstrated as potential inter metal dielectrics (IMD) for sub-micron devices, integrating a stack of two fluorine doped silicon oxide film deposited on a high-density plasma chemical vapor deposition (HDP-CVD) system for gap filling and a plasma-enhanced chemical vapor deposition (PECVD) system for throughput has not been fully investigated. In this research, an excellent and exceptionally stable process was demonstrated for a stack of HDP-CVD FSG and PECVD FSG layers. Cracks that result from multi-level metal technology were eliminated when higher compressive stress PECVD FSG film was implemented as a capping layer. An 11% capacitance reduction was achieved when comparing a stack of FSG films to undoped silicon oxide. No problem occurred for photo, via etching and chemical mechanical polishing of FSG film. The FSG layer stack's via resistance (Rc(-)Via) as well as a full HDP-FSG scheme is comparable. These results are very promising for the integration of FSG films as inter metal dielectric for devices. (C) 2003 Elsevier B.V. All rights reserved.en_US
dc.language.isoen_USen_US
dc.subjecthigh density plasma (HDP)en_US
dc.subjectfluorosilicate glass (FSG)en_US
dc.subjectgap fillen_US
dc.subjectcapacitanceen_US
dc.subjectvia resistance (Rc_Via)en_US
dc.subjectplasma-enhanced chemical vapor deposition (PECVD)en_US
dc.titleIntegration of a stack of two fluorine doped silicon oxide film with ULSI interconnect metallizationen_US
dc.typeArticleen_US
dc.identifier.doi10.1016/j.matchemphys.2003.08.023en_US
dc.identifier.journalMATERIALS CHEMISTRY AND PHYSICSen_US
dc.citation.volume83en_US
dc.citation.issue1en_US
dc.citation.spage150en_US
dc.citation.epage157en_US
dc.contributor.department材料科學與工程學系zh_TW
dc.contributor.departmentDepartment of Materials Science and Engineeringen_US
dc.identifier.wosnumberWOS:000187672000027-
dc.citation.woscount3-
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