完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.author | Cheng, YL | en_US |
dc.contributor.author | Wang, YL | en_US |
dc.contributor.author | Liu, CP | en_US |
dc.contributor.author | Wu, YL | en_US |
dc.contributor.author | Lo, KY | en_US |
dc.contributor.author | Liu, CW | en_US |
dc.contributor.author | Lan, JK | en_US |
dc.contributor.author | Ay, C | en_US |
dc.contributor.author | Feng, MS | en_US |
dc.date.accessioned | 2014-12-08T15:39:44Z | - |
dc.date.available | 2014-12-08T15:39:44Z | - |
dc.date.issued | 2004-01-15 | en_US |
dc.identifier.issn | 0254-0584 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1016/j.matchemphys.2003.08.023 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/27135 | - |
dc.description.abstract | Recently, fluorosilicate glass (FSG) has received much attention for application in microelectronics manufacturing due to its low dielectric constant and stable gap-filling ability. Although FSG films have been demonstrated as potential inter metal dielectrics (IMD) for sub-micron devices, integrating a stack of two fluorine doped silicon oxide film deposited on a high-density plasma chemical vapor deposition (HDP-CVD) system for gap filling and a plasma-enhanced chemical vapor deposition (PECVD) system for throughput has not been fully investigated. In this research, an excellent and exceptionally stable process was demonstrated for a stack of HDP-CVD FSG and PECVD FSG layers. Cracks that result from multi-level metal technology were eliminated when higher compressive stress PECVD FSG film was implemented as a capping layer. An 11% capacitance reduction was achieved when comparing a stack of FSG films to undoped silicon oxide. No problem occurred for photo, via etching and chemical mechanical polishing of FSG film. The FSG layer stack's via resistance (Rc(-)Via) as well as a full HDP-FSG scheme is comparable. These results are very promising for the integration of FSG films as inter metal dielectric for devices. (C) 2003 Elsevier B.V. All rights reserved. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | high density plasma (HDP) | en_US |
dc.subject | fluorosilicate glass (FSG) | en_US |
dc.subject | gap fill | en_US |
dc.subject | capacitance | en_US |
dc.subject | via resistance (Rc_Via) | en_US |
dc.subject | plasma-enhanced chemical vapor deposition (PECVD) | en_US |
dc.title | Integration of a stack of two fluorine doped silicon oxide film with ULSI interconnect metallization | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1016/j.matchemphys.2003.08.023 | en_US |
dc.identifier.journal | MATERIALS CHEMISTRY AND PHYSICS | en_US |
dc.citation.volume | 83 | en_US |
dc.citation.issue | 1 | en_US |
dc.citation.spage | 150 | en_US |
dc.citation.epage | 157 | en_US |
dc.contributor.department | 材料科學與工程學系 | zh_TW |
dc.contributor.department | Department of Materials Science and Engineering | en_US |
dc.identifier.wosnumber | WOS:000187672000027 | - |
dc.citation.woscount | 3 | - |
顯示於類別: | 期刊論文 |