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dc.contributor.authorKer, MDen_US
dc.contributor.authorTseng, TKen_US
dc.date.accessioned2014-12-08T15:39:45Z-
dc.date.available2014-12-08T15:39:45Z-
dc.date.issued2004-01-15en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://dx.doi.org/10.1143/JJAP.43.L33en_US
dc.identifier.urihttp://hdl.handle.net/11536/27136-
dc.description.abstractA novel electrostatic discharge (ESD) protection device with a threshold voltage of similar to0V for complementary metal-oxide semiconductor (CMOS) integrated circuits in sub-quarter-micron CMOS technology is proposed. Quite different to the traditional ESD protection devices, such an active ESD device is originally standing in its turn-on state when the IC is zapped under ESD events. Therefore, such an active ESD device has the fastest turn-on speed and the lowest turn-on voltage to effectively protect the internal circuits with a much thinner gate oxide in future sub-0.1 mum CMOS technology. The proposed active ESD device is fully process-compatible to the general sub-quarter-micron CMOS process.en_US
dc.language.isoen_USen_US
dc.subjectelectrostatic discharge (ESD)en_US
dc.subjectthreshold voltageen_US
dc.subjectactive ESD deviceen_US
dc.subjectleakage currenten_US
dc.titleActive electrostatic discharge (ESD) device for on-chip ESD protection in sub-quarter-micron complementary metal-oxide semiconductor (CMOS) processen_US
dc.typeArticleen_US
dc.identifier.doi10.1143/JJAP.43.L33en_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERSen_US
dc.citation.volume43en_US
dc.citation.issue1A-Ben_US
dc.citation.spageL33en_US
dc.citation.epageL35en_US
dc.contributor.department電機學院zh_TW
dc.contributor.departmentCollege of Electrical and Computer Engineeringen_US
dc.identifier.wosnumberWOS:000220092700011-
dc.citation.woscount2-
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