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dc.contributor.authorHong, Kuo-Cheen_US
dc.contributor.authorChiueh, Hermingen_US
dc.date.accessioned2014-12-08T15:39:49Z-
dc.date.available2014-12-08T15:39:49Z-
dc.date.issued2010en_US
dc.identifier.isbn978-1-4244-7773-9en_US
dc.identifier.issn1548-3746en_US
dc.identifier.urihttp://hdl.handle.net/11536/27209-
dc.description.abstractA wide-bandwidth low-power CT Sigma Delta modulator with 10MHz signal bandwidth is implemented in TSMC 0.18 mu m CMOS process in this paper. To realize such application scenario, the proposed modulator comprises a third-order active-RC loop filter and a 4-bit internal quantizer operating at 320 MHz clock frequency. To reduced clock jitter sensitivity, non-return-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the excess loop delay compensation is achieved by the discrete-time derivator structure. The simulation result achieves above 74-dB SNDR (12 ENOB) over a 10-MHz signal band. The power dissipation is 36mW from a 1.8-V supply and the energy per conversion is 235fJ from post-layout simulation. The proposed circuitry can be utilized in low-power medical imaging and modern wireless communications.en_US
dc.language.isoen_USen_US
dc.titleA 36-mW 320-MHz CMOS Continuous-Time Sigma-Delta Modulator with 10-MHz Bandwidth and 12-bit Resolutionen_US
dc.typeArticleen_US
dc.identifier.journal53RD IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMSen_US
dc.citation.spage725en_US
dc.citation.epage728en_US
dc.contributor.department傳播研究所zh_TW
dc.contributor.departmentInstitute of Communication Studiesen_US
dc.identifier.wosnumberWOS:000287099800181-
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