完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Hong, Kuo-Che | en_US |
dc.contributor.author | Chiueh, Herming | en_US |
dc.date.accessioned | 2014-12-08T15:39:49Z | - |
dc.date.available | 2014-12-08T15:39:49Z | - |
dc.date.issued | 2010 | en_US |
dc.identifier.isbn | 978-1-4244-7773-9 | en_US |
dc.identifier.issn | 1548-3746 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/27209 | - |
dc.description.abstract | A wide-bandwidth low-power CT Sigma Delta modulator with 10MHz signal bandwidth is implemented in TSMC 0.18 mu m CMOS process in this paper. To realize such application scenario, the proposed modulator comprises a third-order active-RC loop filter and a 4-bit internal quantizer operating at 320 MHz clock frequency. To reduced clock jitter sensitivity, non-return-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the excess loop delay compensation is achieved by the discrete-time derivator structure. The simulation result achieves above 74-dB SNDR (12 ENOB) over a 10-MHz signal band. The power dissipation is 36mW from a 1.8-V supply and the energy per conversion is 235fJ from post-layout simulation. The proposed circuitry can be utilized in low-power medical imaging and modern wireless communications. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A 36-mW 320-MHz CMOS Continuous-Time Sigma-Delta Modulator with 10-MHz Bandwidth and 12-bit Resolution | en_US |
dc.type | Article | en_US |
dc.identifier.journal | 53RD IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS | en_US |
dc.citation.spage | 725 | en_US |
dc.citation.epage | 728 | en_US |
dc.contributor.department | 傳播研究所 | zh_TW |
dc.contributor.department | Institute of Communication Studies | en_US |
dc.identifier.wosnumber | WOS:000287099800181 | - |
顯示於類別: | 會議論文 |