Full metadata record
DC FieldValueLanguage
dc.contributor.authorZan, HWen_US
dc.contributor.authorChang, TCen_US
dc.contributor.authorShih, PSen_US
dc.contributor.authorPeng, DZen_US
dc.contributor.authorKuo, PYen_US
dc.contributor.authorHuang, TYen_US
dc.contributor.authorChang, CYen_US
dc.contributor.authorLiu, PTen_US
dc.date.accessioned2014-12-08T15:39:55Z-
dc.date.available2014-12-08T15:39:55Z-
dc.date.issued2004en_US
dc.identifier.issn1099-0062en_US
dc.identifier.urihttp://hdl.handle.net/11536/27266-
dc.identifier.urihttp://dx.doi.org/10.1149/1.1635093en_US
dc.description.abstractA short-channel polycrystalline silicon (poly-Si) thin-film transistor (W/L=10 mum/3 mum) with an ultrathin channel (30 nm) and self-aligned tungsten-clad source/drain structure is demonstrated. With WF6 and SiH4 gas flow ratio of 40/12, selectively deposited tungsten film over 100 nm thick can be easily grown on source/drain regions. As a result, the parasitic source/drain resistance is greatly reduced, leading to improvement of device driving ability. Because tungsten deposition can be carried out at a low processing temperature of 300degreesC, the proposed simple structure is compatible with conventional top-gate structure and can be readily applied to low-temperature poly-Si fabrication. (C) 2003 The Electrochemical Society.en_US
dc.language.isoen_USen_US
dc.titleShort-channel poly-Si thin-film transistors with ultrathin channel and self-aligned tungsten-clad source/drainen_US
dc.typeArticleen_US
dc.identifier.doi10.1149/1.1635093en_US
dc.identifier.journalELECTROCHEMICAL AND SOLID STATE LETTERSen_US
dc.citation.volume7en_US
dc.citation.issue2en_US
dc.citation.spageG31en_US
dc.citation.epageG33en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.department光電工程學系zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.contributor.departmentDepartment of Photonicsen_US
dc.identifier.wosnumberWOS:000188080600014-
dc.citation.woscount0-
Appears in Collections:Articles