标题: | Two-level hierarchical Z-buffer with compression technique for 3D graphics hardware |
作者: | Chen, CH Lee, CY 电子工程学系及电子研究所 Department of Electronics Engineering and Institute of Electronics |
关键字: | 3D graphics hardware;hierarchical Z-buffer;hierarchical Z-buffer compression |
公开日期: | 1-十二月-2003 |
摘要: | The hierarchical Z-buffer is application-invisible and more efficient than the traditional Z-buffer for quickly rejecting hidden geometries. But there are construction and management issues associated with integrating a hierarchical Z-buffer into current graphics hardware. Here we present a two-level hierarchical Z-buffer algorithm, and provide solutions to these issues. Simulation results show that the bandwidth can be reduced by up to 35%. Moreover we propose a dynamic bi-level HZ-buffer compression technique that reduces the buffer size up by to 40%, and for which there is little performance degradation. |
URI: | http://hdl.handle.net/11536/27366 |
ISSN: | 0178-2789 |
期刊: | VISUAL COMPUTER |
Volume: | 19 |
Issue: | 7-8 |
起始页: | 467 |
结束页: | 479 |
显示于类别: | Articles |
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