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dc.contributor.authorWang, SMen_US
dc.contributor.authorWu, CYen_US
dc.date.accessioned2014-12-08T15:40:26Z-
dc.date.available2014-12-08T15:40:26Z-
dc.date.issued2003-09-01en_US
dc.identifier.issn0026-2692en_US
dc.identifier.urihttp://dx.doi.org/10.1016/S0026-2692(03)00129-0en_US
dc.identifier.urihttp://hdl.handle.net/11536/27606-
dc.description.abstractA voltage-controlled negative-differential-resistance device using a merged integrated circuit of two n-channel enhancement-mode MOSFETs and a vertical NPN bipolar transistor, called vertical Lambda-bipolar-transistor (VLBT), is presented for memory application. The new VLBT structure has been developed and its characteristics are derived by a simple circuit model and device physics. A novel single-sided SRAM cell based on the proposed VLBT is presented. Due to the characteristics of the VLBT, it offers better static noise margin and larger driving capability as compared with conventional single-side CMOS memory cell. (C) 2003 Elsevier Science Ltd. All rights reserved.en_US
dc.language.isoen_USen_US
dc.subjectnegative-differential-resistanceen_US
dc.subjectlambda-bipolar-transistoren_US
dc.subjectSRAMen_US
dc.titleAnalysis and design of a new SRAM memory cell based on vertical lambda bipolar transistoren_US
dc.typeArticleen_US
dc.identifier.doi10.1016/S0026-2692(03)00129-0en_US
dc.identifier.journalMICROELECTRONICS JOURNALen_US
dc.citation.volume34en_US
dc.citation.issue9en_US
dc.citation.spage855en_US
dc.citation.epage863en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000184400500014-
dc.citation.woscount0-
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