標題: Analysis on the dependence of layout parameters on ESD robustness of CMOS devices for manufacturing in deep-submicron CMOS process
作者: Chen, TY
Ker, MD
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: energy band diagram;electrostatic discharge (ESD);second breakdown;snapback
公開日期: 1-八月-2003
摘要: The layout dependence on ESD robustness of P40S and PMOS devices has been experimentally investigated in details. A lot of CMOS devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated to find the optimized layout rules for electrostatic discharge (ESD) protection. The main layout parameters to affect ESD robustness of CMOS devices are the channel width, the channel length, the clearance from contact to poly-gate. edge at drain And source regions, the. spacing from,the drain diffusion to the guardring diffusion, and the finger width of each unit finger. Non-uniform turn-on effects have been clearly investigated in, the gate-grounded large-dimension NMOS devices by using EMMI (EMission MIcroscope) observation. The optimized layout parameters have been verified to effectively improve ESD robustness of CMOS devices. The relations between. ESD robustness and the layout parameters have been explained by both transmission line pulsing (TLP) measured data and the, energy band diagrams.
URI: http://dx.doi.org/10.1109/TSM.2003.815200
http://hdl.handle.net/11536/27671
ISSN: 0894-6507
DOI: 10.1109/TSM.2003.815200
期刊: IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
Volume: 16
Issue: 3
起始頁: 486
結束頁: 500
顯示於類別:期刊論文


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