標題: | Substrate-triggered ESD protection circuit without extra process modification |
作者: | Ker, MD Chen, TY 電機學院 College of Electrical and Computer Engineering |
關鍵字: | electrostatic discharge (ESD);ESD protection circuits;gate-coupled technique;substrate-triggered technique |
公開日期: | 1-二月-2003 |
摘要: | A substrate-triggered technique is proposed to improve electrostatic discharge (ESD) protection efficiency of ESD protection circuits without extra salicide blocking and ESD-implantation process modifications in a salicided shallow-trench-isolation CMOS process. By using the layout technique, the whole E.SD protection circuit can be merged into a compact device structure to enhance the substrate-triggered efficiency. This substrate-triggered design can increase ESD robustness and reduce the trigger voltage of the ESD protection device. This substrate-triggered ESD protection circuit with a field oxide device of channel width of 150 mum can sustain a human-body-model ESD level of 3250 V without any extra process modification. Comparing to the traditional ESD protection,design of gate-grounded nMOS (ggnMOS) with silicide-blocking process modification in a 0.25-mum salicided CMOS process, the proposed substrate-triggered design without extra process modification can improve ESD robustness per unit silicon area from the original 1.2 V/mum(2) of ggnMOS to 1.73 V/mum(2). |
URI: | http://dx.doi.org/10.1109/JSSC.2002.807168 http://hdl.handle.net/11536/28118 |
ISSN: | 0018-9200 |
DOI: | 10.1109/JSSC.2002.807168 |
期刊: | IEEE JOURNAL OF SOLID-STATE CIRCUITS |
Volume: | 38 |
Issue: | 2 |
起始頁: | 295 |
結束頁: | 302 |
顯示於類別: | 期刊論文 |