標題: Structure-based specification-constrained test frequency generation for linear analog circuits
作者: Chang, SJ
Lee, CL
Chen, JE
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: test pattern generation;analog IC test;structural test;specification test;Monte-Carlo analysis
公開日期: 1-Jul-2003
摘要: In this paper, an approach to generating the sinusoidal stimulus of the right frequency of a linear analog circuit for testing circuit parameter faults under the constraints of the specifications of the circuit under test (CUT) is presented. This approach considers tolerance bounds due to fabrication process fluctuations of tested parameters using a statistical model and maps them to an accepted region of the observed signature of the CUT. The generated test stimulus is derived based on a proposed testing confidence level. Test generation procedures for both the monotonic and non-monotonic relationships between the signature and the parameter are proposed and demonstrated. The procedures are applied to a continuous time state-variable filter example circuit to show the effectiveness of the methodology.
URI: http://hdl.handle.net/11536/27777
ISSN: 1016-2364
期刊: JOURNAL OF INFORMATION SCIENCE AND ENGINEERING
Volume: 19
Issue: 4
起始頁: 637
結束頁: 651
Appears in Collections:Articles