完整後設資料紀錄
DC 欄位語言
dc.contributor.authorChen, Chih-Lungen_US
dc.contributor.authorLin, Kao-Shouen_US
dc.contributor.authorChang, Hsie-Chiaen_US
dc.contributor.authorFang, Wai-Chien_US
dc.contributor.authorLee, Chen-Yien_US
dc.date.accessioned2014-12-08T15:41:19Z-
dc.date.available2014-12-08T15:41:19Z-
dc.date.issued2009en_US
dc.identifier.isbn978-1-4244-4355-0en_US
dc.identifier.issn1930-8833en_US
dc.identifier.urihttp://hdl.handle.net/11536/28109-
dc.description.abstractIn this paper, a LDPC decoder chip based on CPPEG code construction is presented. The (2048, 1920) irregular LDPC code generated by CP-PEG algorithm has better performance than other PEG-based codes; however, the large check node degrees introduced by high code-rate 15/16 become the implementation bottleneck. To design such a high coderate LDPC decoder, our approach features variable-node-centric sequential scheduling to reduce iteration number, single piplelined decoder architecture to lessen the message storage memory size, as well as optimized check node unit to further compress the register number. Overall 73% message storage memory is saved as compared with traditional architecture. Fabricated in 90nm 1P9M CMOS technology, a test deocder chip could achieve maximum 11.5 Gbps throughput under 1.4V supply voltage with core area of 2.7 x 1.4 mm(2). The energy efficiency is only 0.033 nJ/bit with 5.77 Gbps at 0.8V to meet IEEE 802.15.3c requirements.en_US
dc.language.isoen_USen_US
dc.subjectLDPCen_US
dc.subjectHigh throughputen_US
dc.subjectsequential schedulingen_US
dc.titleA 11.5-Gbps LDPC Decoder Based on CP-PEG Code Constructionen_US
dc.typeProceedings Paperen_US
dc.identifier.journal2009 PROCEEDINGS OF ESSCIRCen_US
dc.citation.spage413en_US
dc.citation.epage416en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000276195800095-
顯示於類別:會議論文