高編碼率之 CP-PEG LDPC 解碼器設計與實做

Abstract

本論文提出了高編碼率之 CP-PEG 低密度同位元碼解碼器。我們使用CP-PEG演算法建造了一個(2048,1920) 非規則低密度同位元碼，錯誤更正能力勝過其他PEG-BASED的演算法所建造的碼。 然而，高字碼15/16將會導致大的Check node degree，也會成為硬體實做上的困難點。我們使用了VSS排程降低解碼圈數，並提出單級管線架構減少訊息的儲存量，同時我們又更進一步最佳化CNU減少所需的暫存器。比起傳統架構，總共73%的訊息可以省去不用儲存。此解碼器在90nm製程下，當供應電壓為1.4V，最高能達到11.5Gbps的解碼速度，晶片的面積是3.78mm2。當供應電壓為0.8V, 能源效率為0.033 nJ/bit 解碼速度為5.77Gbps。根據實驗結果，此CP-PEG解碼器的解碼速度達到IEEE 802.15.3c (1440,1344)碼的要求，並且CP-PEG解碼器擁有與(1440,1344)類似的編碼率。所以我們所提出的方法可以有效的用於設計出高編碼率低密度同位元檢查碼的實做上。

In this thesis, a LDPC decoder chip based on CP-PEG code construction is presented. The (2048, 1920) irregular LDPC code generated by CP-PEG algorithm has better performance than other PEG-based codes; however, the large check node degrees introduced by high code-rate 15/16 become the implementation bottleneck. To design such high code-rate LDPC decoder, our approach features variable-node-centric sequential scheduling to reduce iteration number, single pipelined decoder architecture to lessen the message storage memory size, as well as optimized check node unit to further compress the register number. Overall 73% message storage memory is saved compared to traditional architecture. Fabricated in 90nm CMOS technology, a test decoder chip could achieve maximum 11.5 Gbps throughput under 1.4V supply voltage with core area of 3.78 mm2. While the throughput meets IEEE 802.15.3c (1440, 1344) LDPC code requirement. In addition, CP-PEG (2048, 1920) LDPC code own the similar code rate as the (1440, 1344) code. Thus our proposed methodology is proven to be effective in high code rate decoder design and implementation.