標題: 適用於快閃記憶體之低密度奇偶校驗碼解碼器之設計與實作
Design and Implementation of LDPC Decoder for NAND FLASH Memory
作者: 劉瑋倫
Liu, Wei-Lun
張錫嘉
Chang, Hsie-Chia
電子工程學系 電子研究所
關鍵字: 低密度奇偶校驗碼;快閃記憶體;LDPC;NAND FLASH;Binary LDPC;LDPC Code Construction
公開日期: 2013
摘要: 由於擁有簡單的硬體架構,硬式輸入的 BCH 碼一直被廣泛的使用在現今的NAND 快閃式記憶體系統中。然而,隨著製程技術的縮小化,以及單一單元所能儲存的位元數目增加,NAND 快閃式記憶體的未加工位元錯誤率(Raw Bit Error Rate)也隨之上昇,使得 BCH 碼的解碼效率已不足以應付其需求。在此論文中,我們提出了適用於快閃記憶體之兩位元/三位元軟式輸入低密度奇偶校驗碼(Low Density Parity Check,簡稱 LDPC Codes)。該 LDPC code 能夠提供優於近似規格 BCH 碼之解碼表現,並且能有效的延長快閃記憶體之使用壽命。 我們提出的(9168,8217) LDPC code 是基於可分離循環矩陣(Separable Circulant-Based,SCB)建構而成。同時,藉由進一步應用迴路一致性矩陣 (Cycle-Consistency Matrix, CCM) 的技術,該 LDPC code 內的 bsorbing set 數量得以減少,因此能抑制錯誤地板(error floor)現象的發生。經過模擬,該LDPC code 一直到位元錯誤率 10-9都沒有觀察到錯誤地板現象。此外,在尋找通道訊息之最佳量化值方面,我們使用通訊理論中共同資訊(mutual information)的概念以及模擬退火法以針對特定 LDPC code 找出其最佳量化。利用從實際 TLC快閃記憶體晶片所取得之通道模型,我們進行了 LDPC code 之解碼模擬,並且展示了在使用我們的 LDPC code 以及最佳量化的情況下,TLC 快閃記憶體的壽命比起使用近似規格之 BCH 碼時延長了將近一倍的時間。
In the conventional NAND flash memory system, BCH code has been widely used due to its simplicity in hardware implementation when hard input is adopted. However, as the shrinking of manufacturing process and the increasing number of bits stored per flash memory cell, the raw bit error rate keeps worsening and the BCH code becomes insufficient for providing enough error correcting capacity. In this thesis, 2-bit and 3-bit soft input LDPC decoders are presented to outperform BCH code under the similar code rate, and efficiently prolong the endurance of TLC NAND flash memory. The proposed (9168,8217) LDPC code is constructed from the Separable Circulant-Based LDPC code algorithm. By further adopting the Cycle-Consistency Matrix technique, our LDPC code reduces the number of absorbing sets, and hence lowers the error floor effect. There is no error floor observed before frame error rate (FER) around 10-9. Moreover, concepts of mutual information and simulated annealing are adopted in searching for optimum quantization of channel value in order to provide more accurate input information of LDPC codes. Using distribution data extracted from real TLC NAND flash memory, the simulation of LDPC decoder has been demonstrated and proved that in our approach, the lifetime of TLC NAND flash memory is at least doubled compared with BCH code having the same code rate.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT070050209
http://hdl.handle.net/11536/73648
Appears in Collections:Thesis