標題: | A 3.46 Gb/s (9141,8224) LDPC-based ECC scheme and on-line channel estimation for Solid-State Drive Applications |
作者: | Ho, Kin-Chu Chen, Chih-Lung Liao, Yen-Chin Chang, Hsie-Chia Lee, Chen-Yi 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | LDPC codes;Solid State Drive;NAND Flash memory |
公開日期: | 2015 |
摘要: | As the reliability of NAND Flash memory keeps degrading, Low-Density Parity-Check (LDPC) codes are widely proposed to extend the endurance of Solid State Drive (SSD). However, implementing powerful decoding algorithm such as soft min-sum algorithm with high decoding speed comes along with higher hardware cost. To achieve efficient hardware cost, we propose a multi-strategy ECC scheme which consists of modified gradient descent bit-flipping (MGDBF), hard min-sum, and soft min-sum decoders. The MGDBF decoder aims to correct most of the erroneous codewords with advantages of high decoding throughput and low hardware cost, while the soft min-sum decoder is targeted to correct codewords with large number of errors under moderate decoding throughput and reasonable hardware cost. In addition, we propose a bi-sectional channel estimation technique which enables on-line estimation of distribution to generate accurate soft information for LDPC decoding with low complexity. The ECC codec and the complete Toggle DDR 1.0 NAND interface control circuits are integrated and fabricated in 90nm CMOS process. The throughput of proposed MGDBF decoder achieves 3.46 Gb/s which satisfies the throughput requirement of both toggle DDR 1.0 and 2.0 NAND interfaces. |
URI: | http://hdl.handle.net/11536/134735 |
ISBN: | 978-1-4799-8391-9 |
ISSN: | 0271-4302 |
期刊: | 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) |
起始頁: | 1450 |
結束頁: | 1453 |
顯示於類別: | 會議論文 |