標題: Improving Read Performance of NAND Flash SSDs by Exploiting Error Locality
作者: Liu, Ren-Shuo
Chuang, Meng-Yen
Yang, Chia-Lin
Li, Cheng-Hsuan
Ho, Kin-Chu
Li, Hsiang-Pang
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: NAND flash memory;solid-state drive (SSD);low-density parity-check (LDPC);bit error and cache
公開日期: 四月-2016
摘要: NAND flash-based solid-state drives (SSDs), which can serve as the caches of hard disk drives, have gained popularity in large-scale, high-performance storage. A type of advanced error correction code for SSDs, low-density parity-check (LDPC), is required to mitigate a considerable number of errors in the raw data of NAND flash. However, LDPC imposes read performance overhead due to the complex decoding procedure of LDPC. In this paper, we propose an error-correcting cache (EC-Cache) that exploits "error locality", a characteristic of NAND flash memory, to improve the read performance of SSDs. We use the term "error locality" to refer to the property that the majority of errors in reads to the same flash page appear at the same positions until the page is erased. By caching detected errors, we can correct a significant portion of errors in the requested flash page prior to the LDPC decoding process. This design significantly reduces LDPC decoding overhead because the latency of LDPC is correlated with the number of errors in the input data. We conduct experiments, including flash characterization, LDPC simulation, and SSD simulation, to evaluate EC-Cache. The experimental results demonstrate that EC-Cache can improve the read performance of LDPC-based SSDs by up to 2:6 x.
URI: http://dx.doi.org/10.1109/TC.2014.2345387
http://hdl.handle.net/11536/133451
ISSN: 0018-9340
DOI: 10.1109/TC.2014.2345387
期刊: IEEE TRANSACTIONS ON COMPUTERS
Volume: 65
Issue: 4
起始頁: 1090
結束頁: 1102
顯示於類別:期刊論文