針對三種低密度位元檢測碼與BCH 碼的串接系統之理論探討

Abstract

Bose-Chaudhuri-Hocquenghem (BCH)碼因為其解碼的低複雜度以及其良好的除錯能力，一直被廣泛應用在快閃記憶體作為資料保護之用。近年來multilevel cell (MLC)的製程被發展出來並且應用在快閃記憶體後，雖然有效的增進快閃記憶體的檔案儲存密度，但也使得它在檔案儲存的可靠度降低，這使得MLC無法實踐於現今的許多產品而需要尋求更強大的錯誤更正碼。低密度位元檢測碼(LDPC)因其強大的除錯能力，便成為未來MLC記憶體產品極具潛力的選擇之一。 但要將低密度位元檢測碼應用在MLC快閃記憶體上，需要克服的最大障礙就是它使用疊代解碼而產生錯誤地板現象(Error Floor)。故在這篇論文中，我們針對使用BCH碼當作外部糾錯碼與低密度位元檢測碼當作內部校驗碼的串接系統進行探討，希望能了解這一類型的串接系統是否可改善錯誤地板現象，我們共探討三種串接方案: (1)一個BCH碼串聯多個低密度位元檢測碼; (2)多個BCH碼串聯一個低密度位元檢測碼; (3) 多個BCH碼串聯多個低密度位元檢測碼。我們的分析顯示，在略微損失碼率(code rate)的前提下，使用這兩種錯誤更正碼所組合成的串接系統，的確可以有效的改善錯誤地板現象。

Bose-Chaudhuri-Hocquenghem (BCH) codes have been widely used in flash memories for many years. Yet, in future “high-density” multi-level cell (MLC) flash memories, the raw bit-error-rate (BER) in NAND flash may increase up to around 10−2 at its life time, and hence the conventional hard-decision ECC, such as BCH codes, is no longer sufficient for these memories. Hence, the low-density parity-check (LDPC) codes, as a class of powerful ECCs, become an important candidate for future MLC memories. One of the most significant impediments to the use of LDPC codes in future MLC flash memories is the error floor phenomenon associated with the iterative decoding. So in this thesis, we wish to realize whether the concatenated coding scheme of LDPC codes and BCH codes can eliminate or improve the error floor phenomenon of the LDPC code or not. We thus analyze in this thesis three BCH and LDPC concatenated coding schemes: (1) a single BCH code concatenates with multiple LDPC codes; (2) multiple BCH codes concatenate with a single LDPC code; (3) multiple BCH codes concatenate with multiple LDPC codes. Our analysis shows that the concatenation of the two codes can effectively lower the error floor of the LDPC-only code system at the price of a small rate loss.