標題: | A (21150,19050) GC-LDPC Decoder for NAND Flash Applications |
作者: | Liao, Yen-Chin Lin, Chien Chang, Hsie-Chia Lin, Shu 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Globally-coupled LDPC codes;two-phase local/global iterative decoding;emerging memory ECC |
公開日期: | 1-三月-2019 |
摘要: | In this paper, a (21150, 19050) globally-coupled low-density parity check (GC-LDPC) code designed for NAND flash memories is presented. The proposed LDPC code comprises three disjoint subcodes which can be decoded independently. This highly structural parity check matrix contributes to efficient decoder implementation and flexible decoding flow control. Moreover, a two-phase local/global decoding procedure optimized for the proposed GC-LDPC code is introduced. Scenarios of collaborative decoding that leverages the special code structures are discussed. In the proposed decoder architecture, the pipelined processing elements with scheduling are employed to reduce the critical path and decoding latency as well. Implemented in UMC 65 nm process, the post-layout simulation shows a maximum decoding throughput of 432 Gb/s with the chip area 3.376 mm(2). |
URI: | http://dx.doi.org/10.1109/TCSI.2018.2875311 http://hdl.handle.net/11536/148852 |
ISSN: | 1549-8328 |
DOI: | 10.1109/TCSI.2018.2875311 |
期刊: | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS |
Volume: | 66 |
起始頁: | 1219 |
結束頁: | 1230 |
顯示於類別: | 期刊論文 |