適用於快閃記憶體之二位元軟輸入(9153,8256) 低密度奇偶校驗碼解碼器之設計與實作

Abstract

BCH碼因為硬體架構非常簡單，目前是應用在快閃記憶體系統上錯誤更正碼的主流。面對先進製程的發展與記憶體儲存容量的大幅提升所造成可靠度的降低，以代數解碼演算法為主的BCH碼只能不斷增加校驗碼的數量來提升解碼效能，如此一來也間接地減少資料所能儲存的空間。據此，本論文提出適用於快閃記憶體系統的低密度奇偶校驗碼（Low Density Parity Check, 簡稱LDPC Codes）及其解碼器架構，以二位元軟輸入之LDPC Codes提供在相同編碼率下比BCH碼更好的錯誤更正能力。 由於下世代快閃記憶體的儲存頁碼大小為1024Bytes，我們使用permutation matrix演算法建出編碼率為0.9 的 (9153,8256) LDPC Codes，並利用variable-node-centric sequential scheduling (簡稱VSS)來降低檢查節點運算元之電路複雜度。相較於傳統二階層 MinSum 硬體架構，本論文除有效地節省節點運算元的96%組合電路，藉由VSS，降低校驗節點運算元的76.6%暫存器。使用UMC 90nm製程，所提出的解碼器在工作頻率100MHz與10次解碼次數的情況下，最高吞吐量可達到每秒2.78Gbits。

This thesis proposes a LDPC decoder architecture for NAND flash memory system.BCH code is famous for NAND flash memory system because of its simple hardware architecture. However, advanced technology scale down and more bits of data stored per NAND Flash cell will cause the degradation of reliability. More parity bits are required to improve the correcting capability of BCH code. But this greatly degrades the storage capacity and is infeasible to commercial products. Soft input is required to improve the correcting capability of error correcting code. However, BCH code has only little improvement when soft input is provided. This thesis proposes a 2-bits soft input LDPC decoder, which can outperform BCH code under same code rate. The (9153, 8256) LDPC code is constructed by permutation matrix algorithm with code rate 0.9. The variable-node-centric sequential scheduling (VSS) architecture is adopted and CNU is modified to reduce hardware complexity. Compared to the conventional Min-Sum two-stage pipelined architecture, the proposed architecture can reduce approximately 96% combination circuits of VNU and 76.8% registers. Using 90nm CMOS technology, the maximum throughput can achieve 2.78 Gbps under operating frequency of 100 Mhz with 10 iterations.