具結構性且低錯誤地板的CP-PEG低密度同位元檢查碼之設計

Abstract

PEG演算法已被證明是一種簡單且有效率的方法，可用以設計出好的低密度同位元檢查碼。然而，以PEG演算法建構出來的Tanner圖並無結構性，所對應的同位檢查矩陣裡1的位置完全沒有規則性。在這篇論文裡，我們提出一個以PEG演算法為基礎的通用型方法，可用來建構有結構性的Tanner圖。如同PEG演算法，我們提出的CP-PEG演算法可彈性地選擇參數來建構規則和不規則的Tanner圖。此種硬體導向的低密度同位元檢查碼可減少超大型積體電路實現的複雜度。為了編碼複雜度及錯誤地板的考量，我們所提出的演算法的變型也會被討論到。就位元錯誤率和封包錯誤率而論，模擬結果顯示我們的低密度同位元檢查碼勝過其他以PEG為基礎的低密度同位元檢查碼，而且也優於IEEE 802.16e標準裡所採用的低密度同位元檢查碼。

Progressive edge-growth (PEG) algorithm was proven to be a simple and effective approach to design good LDPC codes. However, the Tanner graph constructed by PEG algorithm is non-structured, leading to the positions of 1's of the corresponding parity check matrix being fully random. In this thesis, a general method based on PEG algorithm is proposed to construct structured Tanner graphs. These hardware-oriented LDPC codes can not only reduce the VLSI implementation complexity but also provide comparable performance. Similar to PEG method, our CP-PEG approach can construct both regular and irregular Tanner graphs with flexible parameters. For considering the encoding complexity and error floor, modifications of proposed algorithm are discussed. Simulation results show that our CP-PEG approach, in terms of bit error rate (BER) or packet error rate (PER), outperforms other PEG-based and IEEE 802.16e LDPC codes.