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dc.contributor.authorHSU, WJen_US
dc.contributor.authorSHEN, WZen_US
dc.date.accessioned2014-12-08T15:04:20Z-
dc.date.available2014-12-08T15:04:20Z-
dc.date.issued1993-10-01en_US
dc.identifier.issn0956-3768en_US
dc.identifier.urihttp://hdl.handle.net/11536/2833-
dc.description.abstractTo implement a multiple output function, one has the option to realise each output with either true logic or complementary logic following with an inverter. In this paper, we propose an efficient algorithm to solve this output phase assignment problem for PLA implementation. Instead of using the double-phase cover minimisation approach, we use a property-checking procedure to estimate the cost of assignments. With the estimated costs, an assignment with minimum cost is chosen. The experimental results show that the proposed algorithm can obtain excellent assignment compared with other approaches.en_US
dc.language.isoen_USen_US
dc.subjectLOGIC OPTIMIZATIONen_US
dc.subjectLOGIC ARRAYSen_US
dc.subjectPHASE ASSIGNMENTen_US
dc.titleEFFICIENT OUTPUT PHASE ASSIGNMENT ALGORITHM FOR PLASen_US
dc.typeArticleen_US
dc.identifier.journalIEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMSen_US
dc.citation.volume140en_US
dc.citation.issue5en_US
dc.citation.spage360en_US
dc.citation.epage366en_US
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:A1993MG19600008-
dc.citation.woscount0-
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