完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | CHANG, LD | en_US |
dc.contributor.author | HSIAO, PY | en_US |
dc.contributor.author | YAN, JT | en_US |
dc.contributor.author | SHEW, PW | en_US |
dc.date.accessioned | 2014-12-08T15:04:20Z | - |
dc.date.available | 2014-12-08T15:04:20Z | - |
dc.date.issued | 1993-10-01 | en_US |
dc.identifier.issn | 0278-0070 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1109/43.256934 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/2835 | - |
dc.description.abstract | In this paper, we present an efficient algorithm for over-the-cell routing in the standard cell layout design technology. Two variations are discussed: one aims to minimize the channel density with fewest tracks over the cells while the other aims to minimize the final channel width. Our algorithm can fit both the two-layer and three-layer routing models. With the two-layer model, there is a single routing layer over the cells for intercell connections. While with the three-layer model, there are two disjoint routing layers over the cells for intercell connections. In our approach, we decompose the problem into two phases: (1) over-the-cell routing and (2) conventional channel routing. The over-the-cell routing phase, which is executed iteratively, consists of two steps, routing over the cells and choosing net segments within the channel. For each iteration in the over-the-cell routing phase, our algorithm removes a net or a subnet which intersects the column with highest column density and route it over the cells according to some prioritized criteria. In comparison with the previous researches, our approach achieved the best effectiveness and has used the least CPU-time. On the average, the execution speed of our router is 163 and 4163 times faster than that of [8] and [9], respectively. Besides, our algorithm can produce results comparable to those produced by the WISER algorithm [10]. | en_US |
dc.language.iso | en_US | en_US |
dc.title | A ROBUST OVER-THE-CELL CHANNEL ROUTER | en_US |
dc.type | Note | en_US |
dc.identifier.doi | 10.1109/43.256934 | en_US |
dc.identifier.journal | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | en_US |
dc.citation.volume | 12 | en_US |
dc.citation.issue | 10 | en_US |
dc.citation.spage | 1592 | en_US |
dc.citation.epage | 1599 | en_US |
dc.contributor.department | 資訊工程學系 | zh_TW |
dc.contributor.department | Department of Computer Science | en_US |
dc.identifier.wosnumber | WOS:A1993MF78400019 | - |
dc.citation.woscount | 5 | - |
顯示於類別: | 期刊論文 |