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dc.contributor.authorYeh, CFen_US
dc.contributor.authorChen, DCHen_US
dc.contributor.authorLu, CYen_US
dc.contributor.authorLiu, Cen_US
dc.contributor.authorLee, STen_US
dc.contributor.authorLiu, CHen_US
dc.contributor.authorChen, TJen_US
dc.date.accessioned2014-12-08T15:41:55Z-
dc.date.available2014-12-08T15:41:55Z-
dc.date.issued2002-10-01en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://hdl.handle.net/11536/28503-
dc.description.abstractLow-temperature ( similar to 300 C) N2O-plasma post-treatment for liquid-phase-deposited (LPD) gate oxide has been proposed for the first time. This treatment successfully takes the place of conventional furnace annealing in O-2 ambient. Results of physicochemical and electrical characteristics shock that N2O-plasma post-treated LPD-SiO2 has a high electrical breakdown field and low interface State density. In addition. N2O-plasma treatment also improves the Si-rich phenomenon of LPD-SiO2. From the comparison with pure N2O-plasma oxidation film, LPD-SiO2 with its short re-oxidation time in N2O plasma plays an important role in relieving interfacial stress. Finally, the novel technology is applied to the gate oxide of low-temperature-processed (LTP) polysilicon thin film transistors (poly-Si TFTs). The device performance reveals excellent electrical characteristics, and the reliability shows a satisfactory result. as well as the gate oxide reliability. It is believed that the N2O-plasma post-treatment not only improves the oxide quality, but also effectively passivates the trap states of poly-Si TFTs.en_US
dc.language.isoen_USen_US
dc.subjectpoly-Si TFTsen_US
dc.subjectN2O-Plasma treatmenten_US
dc.subjectLPD-SiO2en_US
dc.subjectgate oxide reliabilityen_US
dc.subjectliquid phase depositionen_US
dc.titleHighly reliable liquid-phase-deposited SiO2 with nitrous oxide plasma post-treatment for low-temperature-processed polysilicon thin film transistorsen_US
dc.typeArticleen_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERSen_US
dc.citation.volume41en_US
dc.citation.issue10en_US
dc.citation.spage6119en_US
dc.citation.epage6126en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000179893600050-
dc.citation.woscount1-
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