A WIP estimation model for wafer fabrication

Abstract

The standard WIP (work-in-process) level in wafer fabrication is an important parameter which can be used to diminish system disturbances. This parameter can also be used to trigger the decisions of when to release particular wafer lots and how to dispatch them. This paper not only explores the significance of standard WIP in wafer fabrication, but also presents a method, based on the reorder point (ROP) model, to estimate the standard WIP level in front of each workstation. A numerical example illustrates the method's effectiveness. Also, a simulation model of a real-world wafer fabrication factory in Taiwan is constructed and the wafer input control rule, Fixed-WIP, is applied. Results of a single factor experimental design indicate that the standard WIP level estimated in this study achieves a short mean cycle time and an acceptably high mean throughput rate. The phenomenon, occurring throughout this study, in which a lower WIP level does not guarantee a shorter average cycle time in wafer fabrication, is also explored. Results presented herein demonstrate that the ROP-based WIP estimation method is a highly efficient method in deter-mining a safe and reliable standard WIP level during wafer fabrication.