標題: | 晶圓製造廠交期指定模式之構建 The Design of Due-Date Assignment Model for a Wafer Fabrication Factory |
作者: | 鄭照明 Cheng, Chao-Ming 鍾淑馨 Chung, Shu-Hsing 工業工程與管理學系 |
關鍵字: | 晶圓製造;交期指定;固定在製品法;wafer fabrication;due date;Fixed-WIP |
公開日期: | 1995 |
摘要: | 面對目前半導體市場需求大於供給的情況下,半導體晶圓製造廠往 往面臨該如何給定客戶訂單交期以提高系統交期績效之難題。本文之研究 目的即在希望藉由電腦模擬工具之輔助來指定訂單交期,以期提高系統整 體之答交績效。 在瓶頸機器 產出率固定之情況下,若能使系統在製品數量維持穩定,便可控制住系統 流動時間,故而本文以固定在製品量法(Fixed-Wip)作為控制系統在製品 量之手法。進一步利 用由 Little's Law 衍發而出之「計劃在製品量計 算方法」和「計劃完成作業數計算方法」來規劃生產系統之在製品量與完 成作業數。在固定在製品量法之控制下,系統唯有完成既有工件之加工方 允許新工件之投入。因而吾人可以推估各工件之投料時間,提高系統績效 。 模擬結果顯示,本文在實際執行上有其可行性與方便性,且其在 平均延遲、延遲變異、延遲工作比例等各種不同之交期績效指標上的表現 亦十分良好。此外,本法亦提供了一套在固定在製品量法下,如何規劃計 劃在製品量與每日應完成作業數的方法,以為雙界法 (two boundry)於現場派工時之用。 One of the problems that bother the wafer fabrication factories is how toassign the due dates of orders precisely. The objective of this research is todesign the due date assignment model for wafer fabrication factories by the aid of computer simulation. According to Little's law, when the throughput rateof the bottleneckmachines is maintained at a fixed level, the flow time can becontrolled if the system WIP level is fixed. The Fixed-WIP policy thus is usedto controlthe system WIP amount at the lowest level that maximize the throughputof bottleneck machines. For smoothing the material flow and for ensuring theorder requirements being satisfied, the planned-WIP and planed-move amount foreach wafer layer of eachproduct type is derived based on Little's law. Using thetwo kinds of values,the flow time of each product can be estimated that makesthe estimation ofmaterial release time be feasible. The simulation resultsreveal that this model can be executed easily and has good due date performance.The results also demonstrate that this method has good performance on numbers oftardy work, and average value and variance oflateness, when compared with theresults of CON(constant flowtime) and TWK(total processing time). |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#NT840030034 http://hdl.handle.net/11536/60051 |
顯示於類別: | 畢業論文 |