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dc.contributor.authorYu, CMen_US
dc.contributor.authorLin, HCen_US
dc.contributor.authorLin, CYen_US
dc.contributor.authorYeh, KLen_US
dc.contributor.authorHuang, TYen_US
dc.contributor.authorLei, TFen_US
dc.date.accessioned2014-12-08T15:42:06Z-
dc.date.available2014-12-08T15:42:06Z-
dc.date.issued2002-08-01en_US
dc.identifier.issn0038-1101en_US
dc.identifier.urihttp://dx.doi.org/10.1016/S0038-1101(02)00047-3en_US
dc.identifier.urihttp://hdl.handle.net/11536/28602-
dc.description.abstractThin-film transistor (TFT) devices with either a top or a bottom sub-gate were fabricated and characterized. The top sub-gate scheme allows the self-aligned formation of main-gate with respect to the sub-gate. On the other hand, the bottom sub-gate scheme features a self-aligned field-induced drain with a sidewall spacer located on its top to set the effective field-induction-drain (FID) length. Unlike the conventional TFTs, the FID serves to distribute the high drain electric field and thereby eliminates gate-induced drain leakage-like off-state leakage current. Superior device performance is realized with the bottom sub-gate structure. (C) 2002 Elsevier Science Ltd. All rights reserved.en_US
dc.language.isoen_USen_US
dc.subjectthin-film transistoren_US
dc.subjectfield-induced drainen_US
dc.subjectleakageen_US
dc.titleSelf-aligned fabrication of thin-film transistors with field-induced drainen_US
dc.typeArticle; Proceedings Paperen_US
dc.identifier.doi10.1016/S0038-1101(02)00047-3en_US
dc.identifier.journalSOLID-STATE ELECTRONICSen_US
dc.citation.volume46en_US
dc.citation.issue8en_US
dc.citation.spage1091en_US
dc.citation.epage1095en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000177094400004-
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