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dc.contributor.authorLin, JMen_US
dc.contributor.authorYi, KEen_US
dc.contributor.authorChang, YWen_US
dc.date.accessioned2014-12-08T15:42:08Z-
dc.date.available2014-12-08T15:42:08Z-
dc.date.issued2002-08-01en_US
dc.identifier.issn1350-2409en_US
dc.identifier.urihttp://dx.doi.org/10.1049/ip-cds:20020433en_US
dc.identifier.urihttp://hdl.handle.net/11536/28619-
dc.description.abstractThe module placement problem is to determine the co-ordinates of logic modules in a chip such that no two modules overlap and some cost (e.g. silicon area, interconnection length, etc.) is optimised. To shorten connections between inputs and outputs and/or make related modules adjacent, it is desired to place some modules along the specific boundaries of a chip. To deal with such boundary constraints, we explore the feasibility conditions of a B*-tree with boundary constraints and develop a simulated annealing-based algorithm using B*-trees. Unlike most previous work, the proposed algorithm guarantees a feasible B*-tree with boundary constraints for each perturbation. Experimental results show that the algorithm can obtain a smaller silicon area than the most recent work based on sequence pairs.en_US
dc.language.isoen_USen_US
dc.titleModule placement with boundary constraints using B*-treesen_US
dc.typeArticleen_US
dc.identifier.doi10.1049/ip-cds:20020433en_US
dc.identifier.journalIEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMSen_US
dc.citation.volume149en_US
dc.citation.issue4en_US
dc.citation.spage251en_US
dc.citation.epage256en_US
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:000178389700008-
dc.citation.woscount8-
Appears in Collections:Articles


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