Characterization of device degradation of poly-Si TFTs under dynamic operation with drain biased

Abstract

Poly-Si TFTs, which have the similar structures to the MOSFETs, are now having extensive studies for the applications in display system. The high device mobility of these devices enables the possibility to form both the in-pixel switches and integrated circuits with the poly-Si technology, which may greatly reduce the process complexity and fabrication cost. [1] Though recently several kinds of products formed with poly-Si technology had hit the market, the degradation mechanisms of the devices under dynamic operation with the drain biased are still not so clear. Y. Uraoka previously reported that the degradation behavior of the devices under gate AC operation with source/drain grounded is as a result of the swept carriers as the device is about to be turned off. [2] We have also reported that the degradation for the device operated in the off region as the source/drain grounded is because of the discharge behavior in the channel as the gate voltage toggling in the off region. [3] But these stress conditions are still far from the real operation conditions in applications. In this work, the degradation of the poly-Si TFTs under gate dynamic operation with drain biased, which would be much similar to the conditions operated in real applications, is carefully investigated.