BINARY PARTITION ALGORITHMS AND VLSI ARCHITECTURES FOR MEDIAN AND RANK ORDER FILTERING

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DC 欄位	值	語言
dc.contributor.author	LEE, CL	en_US
dc.contributor.author	JEN, CW	en_US
dc.date.accessioned	2014-12-08T15:04:22Z	-
dc.date.available	2014-12-08T15:04:22Z	-
dc.date.issued	1993-09-01	en_US
dc.identifier.issn	1053-587X	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/78.236516	en_US
dc.identifier.uri	http://hdl.handle.net/11536/2867	-
dc.description.abstract	A class of selection algorithms by binary partition is very efficient for median and rank order filtering. A unified discussion of these algorithms is presented. Binary partition algorithms have better time-area complexity than sorting methods. Counting, firing, and updating are three basic steps. A generic structure is proposed to realize these algorithms. They can be implemented by simple and regular modules in VLSI.	en_US
dc.language.iso	en_US	en_US
dc.title	BINARY PARTITION ALGORITHMS AND VLSI ARCHITECTURES FOR MEDIAN AND RANK ORDER FILTERING	en_US
dc.type	Letter	en_US
dc.identifier.doi	10.1109/78.236516	en_US
dc.identifier.journal	IEEE TRANSACTIONS ON SIGNAL PROCESSING	en_US
dc.citation.volume	41	en_US
dc.citation.issue	9	en_US
dc.citation.spage	2937	en_US
dc.citation.epage	2942	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:A1993LY44800018	-
dc.citation.woscount	3	-
顯示於類別：	期刊論文

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