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dc.contributor.authorHsien, LJen_US
dc.contributor.authorChan, YLen_US
dc.contributor.authorChao, TSen_US
dc.contributor.authorJiang, YLen_US
dc.contributor.authorKung, CYen_US
dc.date.accessioned2014-12-08T15:42:17Z-
dc.date.available2014-12-08T15:42:17Z-
dc.date.issued2002-07-01en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://dx.doi.org/10.1143/JJAP.41.4519en_US
dc.identifier.urihttp://hdl.handle.net/11536/28705-
dc.description.abstractMethod for forming ultra-shallow p(+)/n is demonstrated for 0.15 mum p-type metal-oxide-semiconductor field-effect transistor (pMOSFET). The approach includes a capping ultra-thin nitride on the source/drain extension regions followed by a low energy source/drain (S/D) extension implantation. Ultra shallow p(+)/n junctions can be obtained with depth of 27 nm and sheet resistivity of 1007 Omega/square.en_US
dc.language.isoen_USen_US
dc.subjectshallow junctionen_US
dc.subjectnitrideen_US
dc.subjectCMOSen_US
dc.titleUltra-shallow junction formation using implantation through capping nitride layer on source/drain extensionen_US
dc.typeArticleen_US
dc.identifier.doi10.1143/JJAP.41.4519en_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERSen_US
dc.citation.volume41en_US
dc.citation.issue7Aen_US
dc.citation.spage4519en_US
dc.citation.epage4520en_US
dc.contributor.department電子物理學系zh_TW
dc.contributor.departmentDepartment of Electrophysicsen_US
dc.identifier.wosnumberWOS:000177512200022-
dc.citation.woscount0-
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