完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.author | Hsien, LJ | en_US |
| dc.contributor.author | Chan, YL | en_US |
| dc.contributor.author | Chao, TS | en_US |
| dc.contributor.author | Jiang, YL | en_US |
| dc.contributor.author | Kung, CY | en_US |
| dc.date.accessioned | 2014-12-08T15:42:17Z | - |
| dc.date.available | 2014-12-08T15:42:17Z | - |
| dc.date.issued | 2002-07-01 | en_US |
| dc.identifier.issn | 0021-4922 | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1143/JJAP.41.4519 | en_US |
| dc.identifier.uri | http://hdl.handle.net/11536/28705 | - |
| dc.description.abstract | Method for forming ultra-shallow p(+)/n is demonstrated for 0.15 mum p-type metal-oxide-semiconductor field-effect transistor (pMOSFET). The approach includes a capping ultra-thin nitride on the source/drain extension regions followed by a low energy source/drain (S/D) extension implantation. Ultra shallow p(+)/n junctions can be obtained with depth of 27 nm and sheet resistivity of 1007 Omega/square. | en_US |
| dc.language.iso | en_US | en_US |
| dc.subject | shallow junction | en_US |
| dc.subject | nitride | en_US |
| dc.subject | CMOS | en_US |
| dc.title | Ultra-shallow junction formation using implantation through capping nitride layer on source/drain extension | en_US |
| dc.type | Article | en_US |
| dc.identifier.doi | 10.1143/JJAP.41.4519 | en_US |
| dc.identifier.journal | JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS | en_US |
| dc.citation.volume | 41 | en_US |
| dc.citation.issue | 7A | en_US |
| dc.citation.spage | 4519 | en_US |
| dc.citation.epage | 4520 | en_US |
| dc.contributor.department | 電子物理學系 | zh_TW |
| dc.contributor.department | Department of Electrophysics | en_US |
| dc.identifier.wosnumber | WOS:000177512200022 | - |
| dc.citation.woscount | 0 | - |
| 顯示於類別: | 期刊論文 | |

