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dc.contributor.authorWANG, KHen_US
dc.contributor.authorHWANG, TTen_US
dc.contributor.authorCHEN, Cen_US
dc.date.accessioned2014-12-08T15:04:23Z-
dc.date.available2014-12-08T15:04:23Z-
dc.date.issued1993-09-01en_US
dc.identifier.issn0916-8532en_US
dc.identifier.urihttp://hdl.handle.net/11536/2881-
dc.description.abstractReducing communication complexity is a viable approach to multilevel logic synthesis. A communication complexity based approach was proposed previously. In the previous works, only disjoint input decomposition was considered. However, for certain types of circuits, the circuit size can be reduced by using overlapped decomposition. In this paper, we consider overlapped decompositions. Some design issues for overlapped decompositions such as detecting ''globals'' and deriving subfunctions are addressed. Moreover, the Decomposition Don't Cares (DDC) is considered for improving the decomposed results. By using these techniques together, the area and delay of circuits can be further minimized.en_US
dc.language.isoen_USen_US
dc.subjectCOMMUNICATION COMPLEXITYen_US
dc.subjectFUNCTIONAL DECOMPOSITIONen_US
dc.subjectOVERLAPPED DECOMPOSITIONen_US
dc.subjectGLOBALSen_US
dc.subjectDECOMPOSITION DONT CARES (DDC)en_US
dc.titleOVERLAPPED DECOMPOSITIONS FOR COMMUNICATION COMPLEXITY DRIVEN MULTILEVEL LOGIC SYNTHESISen_US
dc.typeArticle; Proceedings Paperen_US
dc.identifier.journalIEICE TRANSACTIONS ON INFORMATION AND SYSTEMSen_US
dc.citation.volumeE76Den_US
dc.citation.issue9en_US
dc.citation.spage1075en_US
dc.citation.epage1084en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.department資訊工程學系zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.contributor.departmentDepartment of Computer Scienceen_US
dc.identifier.wosnumberWOS:A1993LZ41300010-
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