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dc.contributor.authorHsu, WCen_US
dc.contributor.authorLiang, MSen_US
dc.contributor.authorLin, CTen_US
dc.contributor.authorChen, MCen_US
dc.date.accessioned2014-12-08T15:42:27Z-
dc.date.available2014-12-08T15:42:27Z-
dc.date.issued2002-05-01en_US
dc.identifier.issn0021-4922en_US
dc.identifier.urihttp://dx.doi.org/10.1143/JJAP.41.2878en_US
dc.identifier.urihttp://hdl.handle.net/11536/28832-
dc.description.abstractIn this work, we investigate the effect of post-implantation thermal annealing on the quality of thin gate oxides grown on MeV ion-implanted Si substrates for the triple-well structure. The thin gate oxide grown on the MeV ion-implanted Si substrates without post-implantation thermal annealing may contain pinholes, leading to oxide failure at a very low voltage; in addition, the gate oxide has a higher density of interface states, which may result in a low breakdown voltage. With appropriate post-implantation thermal annealing before the growth of the gate oxide, e.g., 1000degreesC for 30 min under the MeV implantation conditions employed in this work, the gate oxide is able to regain its integrity in terms of electrical breakdown voltage.en_US
dc.language.isoen_USen_US
dc.subjecttriple wellen_US
dc.subjecthigh-energy ion implantationen_US
dc.subjectthermal annealingen_US
dc.subjectbreakdown voltageen_US
dc.subjectinterface state densityen_US
dc.titlePost-implantation thermal annealing effect on the gate oxide of triple-well-structureen_US
dc.typeArticleen_US
dc.identifier.doi10.1143/JJAP.41.2878en_US
dc.identifier.journalJAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERSen_US
dc.citation.volume41en_US
dc.citation.issue5Aen_US
dc.citation.spage2878en_US
dc.citation.epage2880en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000176515700016-
dc.citation.woscount0-
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