完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Chang, KM | en_US |
dc.contributor.author | Chung, YH | en_US |
dc.contributor.author | Lin, GM | en_US |
dc.date.accessioned | 2014-12-08T15:42:33Z | - |
dc.date.available | 2014-12-08T15:42:33Z | - |
dc.date.issued | 2002-04-01 | en_US |
dc.identifier.issn | 0021-4922 | en_US |
dc.identifier.uri | http://dx.doi.org/10.1143/JJAP.41.1941 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/28892 | - |
dc.description.abstract | The dynamic stress on low-temperature processed polycrystalline silicon thin-film transistors (poly-Si TFTs) is studied under two different stress conditions. As compared to static stress. the enhanced degradation in poly-Si TFT can be observed in dynamic stress. The enhanced degradation in dynamic stress (V-g = 0-20 V, V-ds = 22 V) is due to (1) the impact ionization effect in the ON state (V-gs = 20 V, V-ds = 22 V), (2) the drain avalanche hot carrier effect in the OFF state (V-gs = 0 V, V-ds = 22 V), and (3) the transient current stressing effect (at the switching period), However, in the stress condition of V-gs = -20 V to 20 V, V-ds = 0 V. both the source and drain regions are equally damaged. As the falling time becomes shorter, the transient current will increase to cause more device degradation near drain. It is also found that the degradation is more serious in short channel device than that in long channel device. As the stress frequency increases, the degradation will be enhanced. Moreover, the reduced degradation under high stress temperature is clue to reduced hot carrier effect under high temperature stressing. | en_US |
dc.language.iso | en_US | en_US |
dc.subject | dynamic stress | en_US |
dc.subject | low-temperature processed polycrystalline silicon thin-film transistors (poly-Si TFTs) | en_US |
dc.subject | impact ionization effect | en_US |
dc.subject | drain avalanche hot carrier effect | en_US |
dc.subject | transient current stressing effect | en_US |
dc.title | Hot carrier induced degradation in the low temperature processed polycrystalline silicon thin film transistors using the dynamic stress | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1143/JJAP.41.1941 | en_US |
dc.identifier.journal | JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS | en_US |
dc.citation.volume | 41 | en_US |
dc.citation.issue | 4A | en_US |
dc.citation.spage | 1941 | en_US |
dc.citation.epage | 1946 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000175703100008 | - |
dc.citation.woscount | 11 | - |
顯示於類別: | 期刊論文 |