複晶矽薄膜電晶體之可靠性研究

Abstract

利用複晶矽薄膜電晶體製作畫素元件及週邊驅動電路並將之積體化於大面積玻璃基座已是未來製作平面液晶顯示器的趨勢，而低溫複晶矽薄膜電晶體的電性與可靠度改善將會是未來重要的關鍵。在本論文中，我們提出一種新的低溫薄膜電晶體結構與動態應力下薄膜電晶體的可靠性研究。 在第一部份中，以兩種不同應力條件的動態應力對低溫製程複晶矽薄膜電晶體的研究。當所謂的Falling Time變短時，通道載子將會變的具高能量且且從通道中被排除，因此元件特性將因這些通道熱載子們而降低，也發現到短通道長度將會比長通道長度還要來的嚴重，此外，隨著應力頻率的增加，衰退的程度越加嚴重，並且在高應力溫度下減少衰退的程度也與減少熱載子效應有關。 在第二部份中，我們提出具有副閘極的新結構。我們發現它的斜率變化與臨界電壓的偏移比傳統薄膜電晶體要來的好，並且我們確信在最適當的通道長度情形下此改善將會更明顯。

Utilizing polycrystalline silicon thin-film transistors (Poly-Si TFTs) as on-glass pixel switching elements and peripheral driver circuits is the future trend for fabricating active-matrix liquid-crystal displays (AMLCDs). The improvement of the electrical characteristic and the reliability of the low-temperature process Poly-Si TFTs are important issues. In this thesis, we proposed a new structure and studied the relibiality of the low-temperature process Poly-Si TFTs using the dynamic stress. In the first part, the dynamic stress on the low-temperature processed polycrystalline silicon thin-film transistors (poly-Si TFTs) is studied under two different stress conditions. As the falling time becomes short, the channel carriers can be accelerated to become hot and repelled from the channel region. Therefore, the device is seriously degraded by these hot channel carriers during the falling transient periods. It is also found that the degradation is more serious in the short channel device than that in the long channel one. In addition, as the stress frequency increases, the degradation is enhanced. Moreover, the reduced degradation under the high stress temperature is also expected to be related to the reduced hot carrier effect under the high temperature stressing. In the second part, we proposed a new structure with two sub-gate region, and we obtained that the slope variation and the threshold voltage shift of new structure were better than that of the conventional TFTs, and we are sure that they will improve substantially for the optimum condition for the new structure.