ELECTRICAL AND MICROSTRUCTURAL CHARACTERISTICS OF TI CONTACTS ON (001)SI

Abstract

An investigation of the electrical and microstructural characteristics of the Ti contact on silicon has been carried out. The presence of As in Ti/n+-Si samples was found to retard the formation of polycrystalline silicide (p-silicide) compared with that in Ti/p+-Si samples with BF2+ implantation. Amorphous interlayers (a-interlayers) were found to be present in both Ti/n-Si and Ti/p-Si samples annealed at temperatures of and lower than 450-degrees-C. Although the Schottky barrier heights (SBH's) vary for about 0.05-0.08 eV for samples annealed over a temperature range from room temperature to 900-degrees-C, SBH's at the a-interlayer/n-Si and a-interlayer/p-Si were measured to be about 0.52-0.54 and 0.59-0.57 eV, respectively. The specific contact resistance (p(c)) in the Ti/n+-Si system was measured to be the lowest with a value of 1.4 X 10(-7) OMEGA cm2 when the a interlayer is present. In Ti/p+-Si system, the minimum rho(c) is about 3 X 10(-7) OMEGA cm2. The variation in contact resistance with annealing temperature for both Ti/n+-Si and Ti/p+-Si samples is correlated to the change in dopant concentration beneath the contacts as well as microstructures. In the temperature regime where the a interlayer is in contact with the silicon substrate, the junction diode leakage current densities (J(leak's)) are considerably lower than those in samples annealed at higher temperatures. The J(leak) at - 6 V reverse bias is lower than 1 nA/cm2. The breakdown voltage is about 14 V (16 V) for the n+/p (p+/n) junction. The thickness of consumed Si is less in samples annealed at low temperature, and the a-interlayer/Si or p-silicide/Si interface is accordingly farther away from the junction as well as the end-of-range defects. The interface of p-silicide/Si is rougher than that of a-interlayer/Si. In addition, the roughness of the p-silicide/Si interface increases with annealing temperature. For both p+/n and n+/p junctions annealed at 900-degrees-C, rough p-silicide/Si interfaces are thought to lead to spiking and increase the leakage currents.