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dc.contributor.authorLi, Yen_US
dc.contributor.authorSze, SMen_US
dc.contributor.authorChao, TSen_US
dc.date.accessioned2014-12-08T15:42:58Z-
dc.date.available2014-12-08T15:42:58Z-
dc.date.issued2002en_US
dc.identifier.issn0177-0667en_US
dc.identifier.urihttp://hdl.handle.net/11536/29116-
dc.identifier.urihttp://dx.doi.org/10.1007/s003660200011en_US
dc.description.abstractWe present a new parallel semiconductor device simulation using the dynamic load balancing approach. This semiconductor device simulation based on the adaptive finite volume method with a posteriori error estimation has been developed and successfully implemented on a 16-PC Linux cluster with a message passing interface library. A constructive monotone iterative technique is also applied for solution of the system of nonlinear algebraic equations. Two different parallel versions of the algorithm to perform a complete device simulation are proposed. The first is a dynamic parallel domain decomposition approach, and the second is a parallel current-voltage characteristic points simulation. This implementation shows that a well-designed load balancing simulation can significantly reduce the execution time up to an order of magnitude. Compared with the measured data, numerical results on various submicron VLSI devices are presented, to show the accuracy and efficiency of the method.en_US
dc.language.isoen_USen_US
dc.subjectDTMOSen_US
dc.subjectdynamic domain decompositionen_US
dc.subjectlinux clusteren_US
dc.subjectload balancingen_US
dc.subjectMOSFETen_US
dc.subjectparallel I-Ven_US
dc.subjectpoints calculationen_US
dc.subjectVLSI device simulationen_US
dc.titleA practical implementation of parallel dynamic load balancing for adaptive computing in VLSI device simulationen_US
dc.typeArticleen_US
dc.identifier.doi10.1007/s003660200011en_US
dc.identifier.journalENGINEERING WITH COMPUTERSen_US
dc.citation.volume18en_US
dc.citation.issue2en_US
dc.citation.spage124en_US
dc.citation.epage137en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.department友訊交大聯合研發中心zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.contributor.departmentD Link NCTU Joint Res Ctren_US
dc.identifier.wosnumberWOS:000178153500004-
dc.citation.woscount75-
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