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dc.contributor.authorHSIEH, PWen_US
dc.contributor.authorTSAI, JMen_US
dc.contributor.authorLEE, CYen_US
dc.date.accessioned2014-12-08T15:04:24Z-
dc.date.available2014-12-08T15:04:24Z-
dc.date.issued1993-08-01en_US
dc.identifier.issn0098-3063en_US
dc.identifier.urihttp://dx.doi.org/10.1109/30.234627en_US
dc.identifier.urihttp://hdl.handle.net/11536/2913-
dc.description.abstractAn area efficient IC for high-throughput median filtering applications is presented in this paper. This IC implements a modified delete-and-insert sorting algorithm which is very efficient for running order statistics applications. In hardware design, we first map the algorithm onto a regular PE structure, where each PE consistis of shift register, comparator, and some control gates. Then we conduct full-custom circuit/layout design of the PE to meet performance requirement. A proto-type chip for 64 input samples is implemented and tested. Results show that clock rate up to 50 MHz can be achieved using a 1.2 mum CMOS double metal technology. Two outstanding features of this IC are: (1) any specified order of input patterns can be produced within one clock cycle; (2) each chip can handle at most 64 data and can be cascaded as the number of sorted data is over 64. Thus this IC releases the bottle-neck of median search in hardware realization for many system designs, making real-time performance achievable.en_US
dc.language.isoen_USen_US
dc.titleAN AREA-EFFICIENT MEDIAN FILTERING IC FOR IMAGE VIDEO APPLICATIONSen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/30.234627en_US
dc.identifier.journalIEEE TRANSACTIONS ON CONSUMER ELECTRONICSen_US
dc.citation.volume39en_US
dc.citation.issue3en_US
dc.citation.spage504en_US
dc.citation.epage509en_US
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:A1993LY44600053-
dc.citation.woscount0-
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