A spread spectrum clock generator for EMI reduction

Abstract

This paper described a new method to generate a spread spectrum clock for the purpose of EMI reduction. This method uses two phase-locked loops (PLL). The output of the first PLL is locked to its input of 14.318-MHz, The VCO in this PLL is used to produce 32 outputs with the same frequency and each with 11.25 degrees phase variation. A digital spread spectrum generator uses these 32 signals to generate the desired spread spectrum signal by phase hopping technique. These two circuits form a spread spect ruin digital PLL (SSDPLL). The second PLL is configured as a conventional frequency synthesizer. It can be programmed to generate the desired frequencies. The second PLL also serves as a low pass filter of the output of the SSDPLL to smooth out frequency variation. This circuit was implemented with a 0.6 mum single poly CMOS process. The active areas of the SSDPLL and the synthesizer are 826 x 396 mum(2) and 790 x 298 mum(2), respectively. The, total power consumption is 99 mW at 3.3 V supply. The peak power of the spread spectrum clock is reduced by 10 dBm at 14.318 MHz output with a 2.34% frequency spreading. The reduction of peak power increases with output frequency.