標題: | Generalized interconnect delay time and crosstalk models: II. Crosstalk-induced delay time deterioration and worst crosstalk models |
作者: | Lee, TGY Tseng, TY Wong, SC Yang, CJ Liang, MS Cheng, HC 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | closed-form model;interconnect;model;crosstalk-enhanced delay;delay;crosstalk;worst case;optimization |
公開日期: | 1-十二月-2001 |
摘要: | New analytical models for estimating crosstalk-induced delay time deterioration and the worst crosstalk models of a coupled interconnect for ramp input waveform are derived. The accuracy of these compact models at various driver resistances, loading capacitances, and input-ramping rates is verified by simulation program with integrated circuit emphasis (SPICE) simulation for the parallel interconnect system. The effects of crosstalk noise on the delay time at various ramp input rise times, for both simultaneous and non-simultaneous switching cases, are discussed here. In this study we show that crosstalk noise will be a limiting factor for future fast transition signals. The results reported herein are useful in the studies of delay time uncertainties due to noise and the interconnect worst-case design. |
URI: | http://hdl.handle.net/11536/29212 |
ISSN: | 0021-4922 |
期刊: | JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS |
Volume: | 40 |
Issue: | 12 |
起始頁: | 6694 |
結束頁: | 6699 |
顯示於類別: | 期刊論文 |