A novel high-performance poly-silicon thin film transistor with a self-aligned thicker sub-gate oxide near the drain/source regions

標題:	A novel high-performance poly-silicon thin film transistor with a self-aligned thicker sub-gate oxide near the drain/source regions
作者:	Chang, KM Chung, YH Lin, GM Lin, JH Deng, CG 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics
關鍵字:	on-off current ratio;photo-masking steps;polysilicon thin-film transistor;self-aligned thicker sub-gate oxide
公開日期:	1-十月-2001
摘要:	In this letter, a novel high-performance poly-silicon thin-film transistor (poly-Si TFT) with a self-aligned thicker sub-gate oxide near the drain/source regions is proposed. Poly-Si TFTs with this new structure have been successfully fabricated and the results demonstrate a higher on-off current ratio of 5.9 x 10(6) and also shows the off-state leakage current 100 times lower than those of the conventional ones at V-GS = -15 V and V-DS = 10 V. Only four photo-masking steps are required and fully compatible with the conventional TFT fabrication processes. This novel structure is a good candidate for the further high-performance large-area device applications.
URI:	http://dx.doi.org/10.1109/55.954915 http://hdl.handle.net/11536/29381
ISSN:	0741-3106
DOI:	10.1109/55.954915
期刊:	IEEE ELECTRON DEVICE LETTERS
Volume:	22
Issue:	10
起始頁:	472
結束頁:	474
顯示於類別：	期刊論文

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