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dc.contributor.authorDung, LRen_US
dc.contributor.authorLee, YLen_US
dc.contributor.authorWu, CMen_US
dc.date.accessioned2014-12-08T15:43:41Z-
dc.date.available2014-12-08T15:43:41Z-
dc.date.issued2001-07-01en_US
dc.identifier.issn0840-8688en_US
dc.identifier.urihttp://hdl.handle.net/11536/29551-
dc.description.abstractDigital signal processing (DSP) has been moving into the era of system-on-chip (SoC) design. Yet, the development of SoC architectures is rather intellectual-property (IP)-based and presents several challenges to designers, notably in the transformation of algorithms and the integration of IP cores. Tams, this paper employs Petri nets to model the DSP algorithms and presents a novel architecture for rapid design of digital signal processing. The architecture features a reconfigurable scheduler to dynamically schedule DSP operations onto processing elements and, thus, tolerates nondeterministic latencies of operations due to communication overhead and memory caching. Using the architecture, the designer can seamlessly plug in different IP cores to explore the alternative solutions and upgrade the architecture by reconfiguring the scheduler.en_US
dc.language.isoen_USen_US
dc.titleA reconfigurable architecture for DSP system-on-chipen_US
dc.typeArticleen_US
dc.identifier.journalCANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING-REVUE CANADIENNE DE GENIE ELECTRIQUE ET INFORMATIQUEen_US
dc.citation.volume26en_US
dc.citation.issue3-4en_US
dc.citation.spage109en_US
dc.citation.epage113en_US
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.identifier.wosnumberWOS:000174357300006-
dc.citation.woscount0-
Appears in Collections:Articles